Raspberry Pi 5
8 GB · quad-core Cortex-A76
BCM2712 PCIe1 · Gen2 x1
Running live on Raspberry Pi 5
Bare metal.
Fully visible.
A deterministic microkernel with its own network stack, storage, TLS, process runtime, PicoScript VM and accelerator paths. No Linux. No libc. No hidden scheduler.
- 4
- dedicated cores
- 14/14
- live selftests
- 32/32
- QEMU smoke
- 3×
- Arc Pro B50 proof
Live framebuffer · Pi 5 · 1920×1080 · kernel-owned telemetry
01BoundedEvery wait has a deadline
02Fail closedNo success-shaped fallbacks
03Event drivenIRQ → FIFO → software IRQ
04ObservableLive state, not marketing state
Hardware fabric
A Pi 5 driving serious PCIe
PIOS has proven a complete switch hierarchy from the BCM2712 PCIe1 root, through a Broadcom/PLX PEX8748, to three Intel Arc Pro B50 GPUs.
FFC
PEX8748
Broadcom / PLX PCIe Gen3
4 × downstream x8
Evidence, not aspiration. Twenty PCIe functions across fifteen buses were enumerated,
BAR0 was sized and mapped, and an Intel Xe2 GMD_ID register was read repeatedly through
the full bridge chain with Bus Master disabled and AER clear.
System architecture
Small kernel. Explicit contracts.
PIOS assigns each core a fixed role and moves work through bounded, generation-checked ownership domains.
Kernel reactor
Network, disk, console and IRQ-driven services. Never blocks.
User management
Preemptive scheduler and FIFO doorbell processing.
User execution
Preemptive EL0 processes with isolated memory.
User execution
Application scheduler and capsule workloads.
IRQ cascades
Hardware IRQs trigger bounded records. Software priority levels execute the work.
Lock-free IPC
SPSC FIFO lanes, explicit publication barriers and sequence-backed wakes.
Capability gates
BARs, DMA spans, processes and storage use generation-backed authority.
Native services
TCP/IP, TLS 1.3, WALFS, PicoScript and the web stack run without an underlying OS.
Accelerators
NEON, VideoCore QPU, Kepler and Intel Xe2 paths with deterministic fallbacks.
Live diagnostics
HDMI, UART, TCP and HTTP expose the same bounded operator surface.
Platform matrix
One set of contracts. Separate target images.
Hardware capabilities vary; kernel invariants do not.
| Target | Architecture | Boot | Networking | Status |
|---|---|---|---|---|
| Raspberry Pi 5 | AArch64 / Cortex-A76 | Stage0 → verified A/B stage2 | GEM + CYW43455 | Live hardware |
| Pi 3 / Zero 2 W | AArch64 / Cortex-A53 | Board-specific stage2 | Native SDIO Wi-Fi | Supported |
| QEMU virt | AArch64 | Direct + stage0 chain | virtio-net | 32/32 smoke |
| Hyper-V | x86_64 | UEFI → PIOS handoff | VMBus / netvsc | Active bring-up |
| Ivy Bridge Xeon | x86_64 | Native UEFI USB | Native PCIe | Boot services |
Documentation
Read the system from first principles
The repository documents current contracts, decisions, evidence and failed experiments.
01
System architecture
Cores, schedulers, IRQs, FIFOs, EL levels and isolation.
Open guide → 02Platforms
Pi hardware, QEMU, PCIe evidence and target differences.
Open guide → 03Network stack
NIC backends, ingress validation, TCP, TLS and capsules.
Open guide → 04Boot & storage
A/B updates, WALFS, keystore and recovery behaviour.
Open guide → 05Decision log
Every significant architectural choice and its owner.
Open log → 06Gotchas
Failed probes, reversals and the traps worth remembering.
Open guide →What comes next
Make the GPUs earn their keep.
Enumeration and Intel MMIO are proven. The next acceptance boundary is useful, contained work—not a green status flag.
Track the work on GitHub- PROVENEnumerate three B50s through PEX8748
- PROVENAssign BAR0 and read Intel Xe2 GMD_ID
- IN PROGRESSGuC, queues and contained DMA completion
- NEXTKnown-answer compute dispatch
- GOALPicoScript Tensor acceleration